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? semiconductor components industries, llc, 2006 august, 2017 ? rev.11 1 publication order number: ar0230cs/d ar0230cs 1/2.7\inch 2.1 mp/full hd digital image sensor general description on semiconductor?s ar0230cs is a 1/2.7?inch cmos digital image sensor with an active?pixel array of 1928hx1088v. it captures images in either linear or high dynamic range modes, with a rolling?shutter readout. it includes sophisticated camera functions such as in?pixel binning, windowing and both video and single frame modes. it is designed for both low light and high dynamic range scene performance. it is programmable through a simple two?wire serial interface. the ar0230cs produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including surveillance and hd video. table 1. key performance parameters parameter typical value optical format 1/2.7?inch (6.6 mm) active pixels 1928(h) x 1088(v) (16:9 mode) pixel size 3.0 m x 3.0 m color filter array rgb bayer shutter type electronic rolling shutter and grr input clock range 6 ? 48 mhz output clock maximum 148.5 mp/s (4?lane hispi) 74.25 mp/s (parallel) output serial hispi 10?, 12?, 14?, 16?, or 20?bit parallel 10?, 12?bit frame rate 1080p 60 fps responsivity 4.0 v/lux?sec snr max 41 db max dynamic range up to 96 db supply voltage i/o 1.8 or 2.8 v digital 1.8 v analog 2.8 v hispi 0.3 v ? 0.6 v (slvs), 1.7 v ? 1.9 v (hivcm) power consumption (typical) 386 mw (linear, 1080p30, 25 c, parallel output) 558 mw (hdr, 1080p30, 25 c, parallel output) operating temperature ?30 c to +85 c ambient package options 10x10 mm 80?pin ibga www. onsemi.com see detailed ordering and shipping information on pag e2 o f this data sheet. ordering information features ? superior low?light performance ? latest 3.0 m pixel with on semiconduc tor dr?pix ? technology with dual conversi on gain ? full hd support at up to 1080p 60 fps for superior video performance ? linear or high dynamic range capture ? optional adaptive local tone mapping (altm) ? pixel or line interleaved t1/t2 output ? support for external mechanical shutter ? on?chip phase?locked loop (pll) oscilla tor ? integrated position?based color and lens shading correction ? slave mode for precise frame?rate control ? stereo/3d camera support ? statistics engine ? data interfaces: four?lane serial high?spee d pixel interface (hispi) differential signalin g (slvs and hiv cm ), or parallel ? auto black level calibration ? high?speed configurable context switchin g ? temperature sensor applications ? video surveillance ? 1080p60 (surveillance) video applications ? high dynamic range imaging ibga80 10 10 case 503an
ar0230cs www. onsemi.com 2 ordering information table 2. available part numbers part number product description orderable product attribute de- scription ? ar0230cssc00suea0?drbr 2 mp 1/3? cis rgb, 0deg cra, ibga package drypack, anti?reflective glass ar0230cssc00sueah3?gevb rgb, 0deg cra, headboard headboard ar0230cssc12suea0?dr 2 mp 1/3? cis rgb, 12deg cra, ibga package drypack ar0230cssc12sueah3?gevb rgb, 12deg cra, headboard headboard ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. see the on semiconductor device nomenclature document ( tnd310/d ) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com . general description the on semiconductor ar0230cs can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. the default mode output is a 1080p?resolution image at 60 frames per second (fps) through the hispi port. in linear mode, it outputs 12?bit or 10?bit a?law compressed raw data, using either the parallel or serial (hispi) output ports. in high dynamic range mode, it outputs 12?bit compressed data using parallel output. in hispi mode, 12? or 14?bit compressed, or 16?bit linearized data may be output. the device may be operated in video (master) mode or in single frame trigger mode. frame_valid and line_valid signals are output on dedicated pins, along with a synchronized pixel clock in parallel mode. the ar0230cs includes additional features to allow application?specific tuning: windowing and offset, auto black level correction, and on?board temperature sensor. optional register information and histogram statistic information can be e mbedded in the first and last 2 lines of the image frame. the ar0230cs is designed to operate over a wide temperature range of ?30 c to +85 c ambient. functional overview the ar0230cs is a progressive?scan sensor that generates a stream of pixel data at a constant frame rate. it uses an on?chip, phase?locked loop (pll) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 48 mhz. the maximum output pixel rate is 148.5 mp/s, corresponding to a clock rate of 74.25 mhz. figure 1 shows a block diagram of the sensor configured in linear mode, and in hdr mode.
ar0230cs www. onsemi.com 3 figure 1. block diagram of ar0230cs adc data row noise correction black level correction test pattern generator pixel defect correction adaptive cd filter digital gain and pedestal a?law compression hispi parallel 12 12 adc data 12 row noise correction black level correction test pattern generator pixel defect correction adaptive cd filter row noise correction digital gain and pedestal motion correction hdr linearization smoothing filter companding or altm hispi parallel 12 16 16 bits 14 or 12 bits 12 bits 12 bits 10 bits user interaction with the sensor is through the two?wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. the core of the sensor is a 2.1 mp active? pixel sensor array. the timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analog?to?digital converter (adc). the output from the adc is a 12?bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). the sensor also offers a high dynamic range mode of operation where multiple images are combined on?chip to produce a single image at 16?bit per pixel value. a compression mode is further offered to allow the 16 bits per pixel to be transmitted to the host system as a 12?bit value with close to zero loss in image quality.
ar0230cs www. onsemi.com 4 slvs0_p slvs0_n slvs1_p slvs1_n slvs2_n slvs2_p slvs3_p slvs3_n slvsc_p slvsc_n flash shutter s addr s data sclk trigger oe_bar test extclk d gnd a gnd v dd_ io v dd v dd_ slvs v dd_ pll v aa v aa_ pix from controller master clock (6?48 mhz) digital i/o power digital core power hispi power pll power analog power analog power reset_bar digital ground analog ground to controlle r notes: 1.5 k 1.5 k v dd_ io v dd v dd_ slvs v dd_ pll v aa v aa_ pix 1. all power supplies must be adequately decoupled 2. on semiconductor recommends a resistor value of 1.5k , but a greater value may be used for slower two?wired speed. 3. the parallel interface output pads can be left unconnected if the serial output interface is used. 4. on semiconductor recommends that 0.1 f and 10 f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on lay out and design considerations. refer to the ar0230cs demo headboard schematics for circuit recommendations. 5. on semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 6. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. figure 2. typical configuration: serial four?lane hispi interface
ar0230cs www. onsemi.com 5 pixclk line_valid frame_valid flash shutter s addr s data sclk trigger oe_bar test extclk d gnd a gnd v dd_ io v dd v dd_ pll v aa v aa_ pix from controller master clock (6?48 mhz) digital i/o power digital core power pll power analog power analog power reset_bar digital ground analog ground to controller notes: 1.5 k 1.5 k v dd_ io v dd v dd_ pll v aa v aa_ pix v dd_ io d out [11:0] figure 3. typical configuration: serial four?lane hispi interface 7. all power supplies must be adequately decoupled. 8. on semiconductor recommends a resistor value of 1.5k , but a greater value may be used for slower two?wired speed. 9. the serial interface output pads and v dd slvs can be left unconnected if the parallel output interface is used. 10. on semiconductor recommends that 0.1 f and 10 f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on lay out and design considerations. refer to the ar0230cs demo headboard schematics for circuit recommendations. 11. on semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 12. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. 13. the extclk input is limited to 6?48 mhz
ar0230cs www. onsemi.com 6 reserved shutter test reset_ bar reserved line_va- lid trigger slvs3_n slvs3_p frame_- valid slvs2_n slvs2_p flash pixclk slvsc_n slvsc_p extclk slvs1_n slvs1_p slvs0_n slvs0_p v dd v dd v dd_ io v dd_ pll d gnd d gnd d gnd d gnd d gnd d gnd a gnd v aa v dd_ slvs v dd d gnd d gnd a gnd v dd v aa s addr v dd_ io d gnd s data s clk d gnd a gnd v aa _pix d out 11 d gnd d out 10 d out 9 a gnd v aa v dd v aa a gnd d gnd d out 8d out 7d out 6d gnd d gnd v dd_ io v dd v dd_ io v dd_ io v dd_ io v dd_ io d out 2d out 1d out 0 v dd d gnd oe_bar a b c d e f g h j 12 3456789 d gnd d gnd d out 5d out 4 d out 3 figure 4. 80?ball ibga package
ar0230cs www. onsemi.com 7 table 3. pin description, 80?ball ibga pin number pin name type description slvs0_p a2 output hispi serial data, lane 0, differential p. slvs1_p a3 output hispi serial data, lane 1, differential p. slvsc_p a4 output hispi serial ddr clock differential p. slvs2_p a5 output hispi serial data, lane 2, differential p. slvs3_p a6 output hispi serial data, lane 3, differential p. v dd _pll b1 power pll power. slvs0_n b2 output hispi serial data, lane 0, differential n. slvs1_n b3 output hispi serial data, lane 1, differential n. slvsc_n b4 output hispi serial ddr clock differential n. slvs2_n b5 output hispi serial data, lane 2, differential n. slvs3_n b6 output hispi serial data, lane 3, differential n. shutter b9 output control for external mechanical shutter. can be left floating if not used. v aa c1, g1, d9, f9 power analog power. a gnd c2, g2, d8, e8, f8 power analog ground. v dd _slvs c4 power 0.3v?0.6v or 1.7v ? 1.9v port to hispi output driver. set the high_vcm (r0x306e[9]) bit to 1 when configuring vdd_slvs to 1.7 ? 1.9v. v dd c5, j5, a9, h9, a7, d1, f1 power digital power. reserved c9, f7 d gnd b7, c7, d7, e7, g7, b8, c8, g8, d2, e2, f2, h2, c3, g3, h3, c6, j6 power digital ground. extclk d3 input external input clock. pixclk d4 output pixel clock out. dout is valid on rising edge of this clock. s addr d5 input two?wire serial address select. 0: 0x20. 1: 0x30 trigger d6 input exposure synchronization input. v aa _pix e9 power pixel power. v dd _io e1, h1, j2, j7, a8, g9, j9 power i/o supply power. s data e3 i/o two?wire serial data i/o. flash e4 output flash control output. frame_valid e5 output asserted when dout frame data is valid. s clk e6 input two?wire serial clock input. d out 11 f3 output parallel pixel data output (msb) d out 10 f4 output parallel pixel data output. d out 9 f5 output parallel pixel data output. line_valid f6 output asserted when dout line data is valid. d out 8 g4 output parallel pixel data output. d out 7 g5 output parallel pixel data output. d out 6 g6 output parallel pixel data output. d out 5 h4 output parallel pixel data output. d out 4 h5 output parallel pixel data output. d out 3 h6 output parallel pixel data output. reset_bar h7 input asynchronous reset (active low). all settings are restored to factory de- fault. test h8 input. manufacturing test enable pin (connect to dgnd).
ar0230cs www. onsemi.com 8 table 3. pin description, 80?ball ibga (continued) pin number description type pin name d out 2 j1 output parallel pixel data output. d out 1 j3 output parallel pixel data output. d out 0 j4 output parallel pixel data output (lsb) oe_bar j8 input output enable (active low). pixel data format pixel array structure while the sensor?s format is 1928 x 1088, additional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. the pixel adjustment is always performed for monochrome or color versions. the active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. not all dummy pixels or barrier pixels can be read out. figure 5. pixel array description 1944 1116 light dummy pixel active pixel 10 barrier + 4 border pixels 2 barrier + 6 border pixels 10 barrier + 4 border pixels 2 barrier + 6 border pixels 1928 x 1088 5.78 mm x 3.26 mm
ar0230cs www. onsemi.com 9 figure 6. pixel color pattern detail (top right corner) . . . . . . ... g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b column readout direction active pixel (0,0) array pixel (0,0) row readout direction r g r g r g default readout order by convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see figure 6 ). this reflects the actual layout of the array on the die. also, the first pixel data read out of the sensor in default condition is that of pixel (10, 14). when the sensor is imaging, the active surface of the sensor faces the scene as shown in figure 7. when the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced as shown in figure 7. sensor (rear view) lens scene row readout order column readout order pixel (0.0) figure 7. imaging a scene
ar0230cs www. onsemi.com 10 features overview for a complete description, recommendations, and usage guidelines for product features, refer to the ar0230cs developer guide. 3.0 m dual conversion gain pixel to improve the low light performance and keep the high dynamic range, a large (3.0um) dual conversion gain pixel is implemented for better image optimization. with a dual conversion gain pixel, the conversion gain of the pixel may be dynamically changed to better adapt the pixel response based on dynamic range of the scene. this gain can be switched manually or automatically by an auto exposure control module. hdr by default, the sensor powers up in hdr mode. the hdr scheme used is multi?exposure hdr. this allows the sensor to handle up to 96 db of dynamic range. in hdr mode, the sensor sequentially captures two exposures by maintaining two separate read and reset pointers that are interleaved within the rolling shutter readout. the intermediate pixel values are stored in line buffers while waiting for the two exposure values to be present. as soon as a pixel?s two exposure values are available, they are combined to create a linearized 16?bit value for each pixel?s response. the exposure ratio may be set to 4x, 8x, 16x, or 32x. depending on whether hispi or parallel mode is selected, the full 16 bit value may be output, it can be compressed to 12 bits using adaptive local tone mapping (altm), or companded to 12 or 14 bits. options to output t1 only, t2 only, or pixel interleaved data are also available. individual exposures may be read out in a line interleaved mode as described in the t1/t2 line interleaved mode section. resolution the active array supports a maximum of 1928x1088 pixels to support 1080p resolution. utilizing a 3.0um pixel will result in an optical format of 1/2.7?inch (approximately 6.6mm diagonal). frame rate at full (1080p) resolution, the ar0230cs is capable of running up to 3060 fps. image acquisition mode the ar0230cs supports two image acquisition modes: ? electronic rolling shutter (ers) mode this is the normal mode of operation. when the ar0230cs is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ers. when ers mode is in use, timing and control logic within the sensor sequences through the rows of the array , resetting and then reading each row in turn. in the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. the integration (exposure) time is controlled by varying the time between row reset and row readout. for each row in a frame, the time between row reset and row readout is the same, leading to a uniform integration time across the frame. when the integration time is changed (by using the two?wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the ar0230cs switches cleanly from the old integration time to the new while only generating frames with uniform integration. see ?changes to integration time? in the ar0230cs register reference. ? global reset mode. this mode can be used to acquire a single image at the current resolution. in this mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the ar0230cs provides control signals to interface to that shutter. the benefit of using an external electromechanical shutter is that it eliminates the visual artifacts associated with ers operation. visual artifacts arise in ers operation, particularly at low frame rates, because an ers image effectively integrates each row of the pixel array at a different point in time. embedded data and statistics the ar0230cs has the capability to output image data and statistics embedded within the frame timing. there are two types of information embedded within the frame readout. ? embedded data: if enabled, these are displayed on the two rows immediately before the first active pixel row is displayed. ? embedded statistics: if enabled, these are displayed on the two rows immediately after the last active pixel row is displayed.
ar0230cs www. onsemi.com 11 multi?camera synchronization the ar0230cs supports advanced line synchronization controls for multi?camera (stereo) support. slave mode the slave mode feature of the ar0230cs supports triggering the start of a frame readout from an input signal that is supplied from an external asic. the slave mode signal allows for precise control of frame rate and register change updates. context switching and register updates the user has the option of using the highly configurable context memory, or a simplified implementation in which only a subset of registers is available for switching. the ar0230 supports a highly configurable context switching ram of size 256 x 16. within this context memory, changes to any register may be stored. the register set for each context must be the same, but the number of contexts and registers per context are limited only by the size of the context memory. alternatively, the user may switch between two predefined register sets a and b by writing to a context switch change bit. when the context switch is configured to context a the sensor will reference the context a registers. if the context switch is changed from a to b during the readout of frame n, the sensor will then reference the context b coarse_integration_time registers in frame n+1 and all other context b registers at the beginning of reading frame n+2. the sensor will show the same behavior when changing from context b to context a. the registers listed in table 4 are context?switchable: table 4. list of configurable registers for context a and context b context a context b register description register description coarse_integration_time coarse_integration_time_cb line_length_pck ine_length_pck_cb frame_length_lines frame_length_lines_cb row_bin row_bin_cb col_bin col_bin_cb fine_gain fine_gain_cb coarse_gain coarse_gain_cb x_addr_start x_addr_start_cb y_addr_start y_addr_start_cb x_addr_end x_addr_end_cb y_addr_end y_addr_end_cb y_odd_inc y_odd_inc_cb x_odd_inc x_odd_inc_cb green1_gain green1_gain_cb blue_gain blue_gain_cb red_gain red_gain_cb green2_gain green2_gain_cb global_gain global_gain_cb operation_mode_ctrl operation_mode_ctrl_cb bypass_pix_comb bypass_pix_comb_cb motion compensation/dlo in typical multi?exposure hdr systems, motion artifacts can be created when objects move during the t1 or t2 integration time. when this happens, edge artifacts can potentially be visible and might look like a ghosting effect. to correct this, the ar0230cs has special 2d motion compensation circuitry that detects motion artifacts and corrects the image. the motion compensation feature can be optionally enabled by register write. additional parameters are available to control the extent of motion detection and correction as per the requirements of the specific application.
ar0230cs www. onsemi.com 12 tone mapping real?world scenes often have a very high dynamic range (hdr) that far exceeds the electrical dynamic range of the imager. dynamic range is defined as the luminance ratio between the brightest and the darkest objects in a scene. even though the ar0230cs can capture full dynamic range images, the images are still limited by the low dynamic range of display devices. today?s typical lcd monitor has a contrast ratio around 1,000:1 while it is not atypical for an hdr image having a contrast ratio of around 250,000:1. therefore, in order to reproduce hdr images on a low dynamic range display device, the captured high dynamic range must be compressed to the available range of the display device. this is commonly called tone mapping. the ar0230cs has implemented an adaptive local tone mapping (altm) feature to reproduce visually appealing images that increase the local contrast and the visibility of the images. adaptive color difference (adacd) noise filtering a good noise reduction filter will remove noise from an image while retaining as much image detail as possible. to retain image detail, the noise reduction filter must adapt to the image signal. to remove noise, the noise reduction filter must adapt to the noise level of the image signal. the key is to remove the appropriate amount of noise. over?filtering will cause image blurring while under?filtering will leave noise in the image. the adacd algorithm relies on a noise model derived from characterization data to aid in separating noise from signal. the ar0230cs adacd algorithm performs pixel?by?pixel color noise correction for each of the red, blue, and green color planes. each pixel is corrected based on surrounding pixel values on the same color plane and a noise model. the noise model is based on characterization data, and takes into account applied analog gain. fast mode switch (combi mode) to facilitate faster switching between linear and hdr modes, the ar0230cs includes a combi mode feature. when enabled, combi mode loads a single (hdr) sequencer. when switching from hdr to linear modes, the sequencer remains the same, but only the t1 image is output. while not optimized for linear mode operation, it allows faster mode switching as a new sequencer load is not needed. switching between modes may result in the output of one bad frame. analog/digital gain a programmable analog gain of 1.5x to 12x (hdr) and 1.5x to 16x (linear) applied simultaneously to all color channels will be featured along with a digital gain of 1x to 16x that may be configured on a per color channel basis. skipping/binning modes the ar0230cs supports subsampling. subsampling allows the sensor to read out a smaller set of active pixels by either skipping, binning, or summing pixels within the readout window. horizontal binning is achieved in the digital readout. the sensor will sample the combined 2x adjacent pixels within the same color plane. vertical row binning is applied in the pixel readout. row binning can be configured as 2x rows within the same color plane. pixel skipping can be configured up to 2x in both the x?direction and y?direction. skipping pixels in the x?direction will not reduce the row time. skipping pixels in the y direction will reduce the number of rows from the sensor effectively reducing the frame time. skipping will introduce image artifacts from aliasing. the ar0230cs supports row wise vertical binning. row wise vertical summing is not supported. clocking options the sensor contains a phase?locked loop (pll) that is used for timing generation and control. the required vco clock frequency is attained through the use of a pre?pll clock divider followed by a multiplier. the pll multiplier should be an even integer. if an odd integer (m) is programmed, the pll will default to the lower (m?1) value to maintain an even multiplier value. the multiplier is followed by a set of dividers used to generate the output clocks required for the sensor array, the pixel analog and digital readout paths, and the output parallel and serial interfaces. use of the pll is required when using the hispi interface. temperature sensor the ar0230cs sensor has a built?in pta t?based temperature sensor, accessible through registers, that is capable of measuring die junction temperature. the value read out from the temperature sensor register is an adc output value that needs to be converted downstream to a final temperature value in degrees celsius. since the ptat device characteristic response is quite linear in the temperature range of operation required, a simple linear function can be used to convert the adc output value to the final temperature in degrees celsius. a single reference point will be made available via register read as well as a slope for back?calculating the junction temperature value. an error of +/?5% or better over the full specified operating range of the sensor is to be expected. silicon / firmware / sequencer revision information a revision register will be provided to read out (via i c) silicon and sequencer/otpm revision information. this will be helpful to distinguish among dif ferent lots of material if there are future otpm or sequencer revisions. lens shading correction the latest lens shading correction algorithm will be included for potential low z height applications. companding the 16?bit linearized hdr image may be compressed to 12? or 14? bits using on?chip companding. this is useful if
ar0230cs www. onsemi.com 13 on?chip al tm will not be used and the isp cannot handle 16 bit data. compression when the ar0230cs is configured for linear mode operation, the sensor can optionally compress 12?bit data to 10?bit using a?law compression. the a?law compression is disabled by default. packaging the ar0230cs will be offered in a 10x10 80?ibga package (parallel and hispi). the package will have anti?reflective coating on both sides of the cover glass. parallel interface the parallel pixel data interface uses these output?only signals: ? frame_valid ? line_valid ? pixclk ? d out [11:0] the parallel pixel data interface is disabled by default at power up and after reset. it can be enabled by programming r0x301a. when the parallel pixel data interface is in use, the serial data output signals can be left unconnected. high speed serial pixel (hispi) interface the hispi interface supports three protocols, streaming?s, streaming?sp, and packetized sp. the streaming protocols conform to a standard video application where each line of active or intra?frame blanking provided by the sensor is transmitted at the same length. the packetized sp protocol will transmit only the active data ignoring line?to?line and frame?to?frame blanking data. the hispi interface building block is a unidirectional differential serial interface with four data and one double data rate (ddr) clock lanes. one clock for every four serial data lanes is provided for phase alignment across multiple lanes. the ar0230cs supports serial data widths of 10, 12, 14, 16, or 20 bits on one, two, or four lanes. the specification includes a dll to compensate for differences in group delay for each data lane. the dll is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. once the dll has gained phase lock, each lane can be delayed in 1/8 unit interval (ui) steps. this additional delay allows the user to increase the setup or hold time at the receiver circuits and can be used to compensate for skew introduced in pcb design. delay compensation may be set for clock and/or data lines in the hispi_timing register r0x31c0. if the dll timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x0000 to reduce jitter, skew, and power dissipation. sensor control interface the two?wire serial interface bus enables read/write access to control and status registers within the ar0230cs. the interface protocol uses a master/slave model in which a master controls one or more slave devices. the sensor acts as a slave device. the master generates a clock (s clk ) that is an input to the sensor and is used to synchronize transfers. data is transferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd _io off?chip by a 1.5k resistor. either the slave or master device can drive s data low?the interface protocol determines which device is allowed to drive s data at any given time. the two?wire serial interface can run at 100 khz or 400 khz. t1/t2 line interleaved mode the ar0230cs has the capability to output the t1 and t2 exposures separately, in a line interleaved format. the purpose of this is to enable of f chip hdr linear combination and processing. see the ar0230cs developer guide for more information.
ar0230cs www. onsemi.com 14 0 10 20 30 40 50 350 450 550 650 750 850 950 1050 wavelength (nm) quantum efficiency (%) blue red 1150 60 70 80 green (b) green (r) figure 8. typical spectral characteristics electrical specifications unless otherwise stated, the following specifications apply under the following conditions: v dd = 1.8v ? 0.10/+0.15; v dd _io = v dd _pll = v aa = v aa _pix = 2.8v 0.3v; v dd _slvs = 0.4v ? 0.1/+0.2; t a = ?30 c to +85 c?40 c to +105 c; output load = 10pf; frequency = 74.25 mhz; hispi off. two?wire serial register interface the electrical characteristics of the two?wire serial register interface (s clk , s data ) are shown in figure 9 and table 5. figure 9. two?wire serial bus timing parameters t t t f s data s clk ps su;sto buf hd;sta su;sta high hd;dat hd;sta sr t t t t t s t r t f t r su;dat t note: read sequence: for an 8?bit read, read waveforms start after write command and register address are issued. t low
ar0230cs www. onsemi.com 15 table 5. two?wire serial bus characteristics (f extclk = 27 mhz;v dd = 1.8v; v dd _ io = 2.8v;v aa _pix = 2.8v;v dd _ pll = 2.8v; t a = 25 c) parameter symbol standard mode fast mode unit s clk clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 4.0 ? 0.6 ? s low period of the sclk clock t low 4.7 ? 1.3 ? s high period of the sclk clock t high 4.0 ? 0.6 ? s set?up time for a repeated start con- dition t su;sta 4.7 ? 0.6 ? s data hold time t hd;dat 0 4 3.45 5 0 6 0.9 5 s data set?up time t su;dat 250 ? 100 6 ? ns rise time of both s data and s clk sig- nals t r ? 1000 20 + 0.1cb 7 300 ns fall time of both s data and s clk signals t f ? 300 20 + 0.1cb 7 300 ns set?up time for stop condition t su;sto 4.0 ? 0.6 ? s bus free time between a stop and start condition t buf 4.7 ? 1.3 ? s capacitive load for each bus line cb ? 400 ? 400 pf serial interface input pin capacitance cin_si ? 3.3 ? 3.3 pf s data max load capacitance cload_sd ? 30 ? 30 pf s data pull?up resistor rsd 1.5 4.7 1.5 4.7 k 1. this table is based on i c standard (v2.1 january 2000). philips semiconductor. 2. two?wire control is i c?compatible. 3. all values referred to v ihmin = 0.9 v dd and v ilmax = 0.1v dd levels. sensor exclk = 27 mhz. 4. a device must internally provide a hold time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the device does not stretch the low period ( t low) of the s clk signal. 6. a fast?mode i c?bus device can be used in a standard?mode i 2 c?bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard?mode i 2 c?bus specification) before the s clk line is released. 7. cb = total capacitance of one bus line in pf. i/o timing by default, the ar0230cs launches pixel data, fv, and lv with the falling edge of pixclk. the expectation is that the user captures d out [11:0], fv, and lv using the rising edge of pixclk. see figure 10 below and table 6 for i/o timing (ac) characteristics.
ar0230cs www. onsemi.com 16 figure 10. i/o timing diagram t r extclk pixclk data[11:0] line_valid/ frame_valid t tt p rp fp t extclk 90% 10% 90% 10% pfl t pll t plh pfh t t frame_valid leads line_valid by 6 pixclks pd t frame_valid trails line_valid by 6 pixclks pxl_o pxl_1 pxl_2 pxl_n table 6. i/o timing characteristics symbol definition condition min typ max unit f extclk1 s input clock frequency 6 ? 48 mhz t extclk1 input clock period 20.8 ? 166 ns t r input clock rise time ? 3 ? ns t f input clock fall time ? 3 ? ns t rp pixclk rise time 2 3.5 5 ns t fp pixclk fall time 2 3.5 5 ns clock duty cycle 45 50 55 % t cp extclk to pixclk propagation delay nominal voltages, pll disabled 10 14 18 ns f pixclk pixclk frequency default, nominal voltages 6 74.25 mhz t pd pixclk to data valid default, nominal voltages 3.6 5.5 9.5 ns t pfh pixclk to fv high default, nominal voltages 2.9 5.3 9 ns t plh pixclk to lv high default, nominal voltages 2.9 5 9 ns t pfl pixclk to fv low default, nominal voltages 2.9 5 9 ns t pll pixclk to lv low default, nominal voltages 2.9 4.8 9 ns c load output load capacitance ? <10 ? pf c in input pin capacitance ? 2.5 ? pf 1. i/o timing characteristics are measured under the following conditions: ? temperature is 255c ambient ? 10 pf load ? 1.8v i/o supply voltage
ar0230cs www. onsemi.com 17 dc electrical characteristics the dc electrical characteristics are shown in the tables below. table 7. dc electrical characteristics definition symbol condition min typ max unit v dd core digital voltage 1.7 1.8 1.95 v v dd_ io i/o digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 v v aa analog voltage 2.5 2.8 3.1 v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v dd_ pll pll supply voltage 2.5 2.8 3.1 v v dd _slvs hispi supply voltage 0.3 0.4 0.6 v v ih input high voltage v dd _io*0.7 ? ? v v il input low voltage ? ? v dd _io*0.3 v i in input leakage current no pull?up resistor; v in = v dd_ io or d gnd 20 ? ? a v oh output high voltage v dd _io?0.3 ? ? v v ol output low voltage ? ? 0.4 v i oh output high current at specified v oh ?22 ? ? ma i ol output low current at specified v ol ? ? 22 ma caution: stresses greater than those listed in table 8 may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. table 8. absolute maximum ratings symbol definition condition typ max unit v dd_ max core digital voltage ?0.3 2.4 v v dd_ io _ max i/o digital voltage ?0.3 4 v v aa_ max analog voltage ?0.3 4 v v aa_ pix pixel supply voltage ?0.3 4 v v dd_ pll pll supply voltage ?0.3 4 v v dd_ slvs _ max hispi i/o digital voltage ?0.3 2.4 v t st storage temperature ?40 85 c 1. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 9. 1080p30 hdr (altm) 74 mhz parallel 2.8v definition condition symbol voltage min typ max digital operating current streaming 1080p30 i dd 1.8 90 175 220 i/o digital operating current streaming 1080p30 i dd _io 2.8 10 30 50 analog operating current streaming 1080p30 i aa 2.8 35 45 85 pixel supply current streaming 1080p30 i aa _pix 2.8 2 4 7 pll supply current streaming 1080p30 i dd _pll 2.8 5.5 6.2 7 power (mw) 309 557.76 813.2 2. operating currents are measured in ma at the following conditions: ? v aa = v aa_ pix = v dd_ pll = v dd_ io = 2.8 v ? v dd = 1.8 v ? pll enabled and pixclk = 74.25 mhz ? low power mode enabled ? t a = 25 c
ar0230cs www. onsemi.com 18 table 10. 1080p30 linear 74mhz parallel 2.8v definition condition symbol voltage min typ max digital operating current streaming 1080p30 i dd 1.8 75 107 145 i/o digital operating current streaming 1080p30 i dd _io 2.8 10 30 50 analog operating current streaming 1080p30 i aa 2.8 20 30 50 pixel supply current streaming 1080p30 i aa _pix 2.8 1 3 7 pll supply current streaming 1080p30 i dd _pll 2.8 5.5 6.2 7 power (mw) 237.2 386.36 580.2 3. operating currents are measured in ma at the following conditions: ? v aa = v aa _pix = v dd _pll = v dd _io =2.8 v ? v dd = 1.8 v ? pll enabled and pixclk = 74.25 mhz ? low power mode enabled ? t a = 25 c table 11. 1080p30 hdr (altm) 74mhz parallel 1.8v definition condition symbol voltage min typ max digital operating current streaming 1080p30 i dd 1.8 90 175 220 i/o digital operating current streaming 1080p30 i dd _io 1.8 10 20 30 analog operating current streaming 1080p30 i aa 2.8 35 45 85 pixel supply current streaming 1080p30 i aa _pix 2.8 2 4 7 pll supply current streaming 1080p30 i dd _pll 2.8 5.5 6.2 7 power (mw) 299 509.76 727.2 4. operating currents are measured in ma at the following conditions: ? v aa = v aa _pix = v dd _pll = 2.8 v ? v dd = v dd _io= 1.8 v ? pll enabled and pixclk = 74.25 mhz ? low power mode enabled ? t a = 25 c table 12. 1080p30 linear 74 mhz parallel 1.8v definition condition symbol voltage min typ max digital operating current streaming 1080p30 i dd 1.8 75 107 145 i/o digital operating current streaming 1080p30 i dd _ oio 1.8 10 20 30 analog operating current streaming 1080p30 i aa 2.8 20 30 50 pixel supply current streaming 1080p30 i dd _pix 2.8 1 3 7 pll supply current streaming 1080p30 i dd _pll 2.8 5.5 6.2 7 power (mw) 227.2 338.36 494.2 5. operating currents are measured in ma at the following conditions: ? v aa = v aa _pix = v dd _pll =2.8 v ? v dd = v dd _io= 1.8 v ? pll enabled and pixclk = 74.25 mhz ? low power mode enabled ? t a = 25 c table 13. 1080p30 hdr (altm) 74 mhz hispi slvs (low power mode) definition condition symbol voltage min typ max digital operating current streaming 1080p30 i dd 1.8 145 175 235 analog operating current streaming 1080p30 i aa 2.8 25 46 65 pixel supply current streaming 1080p30 i aa _ pix 2.8 1 4 7 pll supply current streaming 1080p30 i dd _pll 2.8 6 7.4 8.5 slvs supply current streaming 1080p30 i dd _slvs 0.4 3 9 14 power (mw) 351.8 479.32 654
ar0230cs www. onsemi.com 19 6. operating currents are measured in ma at the following conditions: ? v aa = v aa _pix = v dd _pll = 2.8 v ? v dd = v dd _io= 1.8 v ? v dd _slvs= 0.4v ? pll enabled and pixclk = 37.125 mhz ? 4?lane hispi mode ? low power mode enabled ? t a = 25 c table 14. 1080p30 linear 74 mhz hispi slvs definition condition symbol voltage min typ max digital operating current streaming 1080p30 i dd 1.8 75 115 155 analog operating current streaming 1080p30 i aa 2.8 20 30 50 pixel supply current streaming 1080p30 i aa _ pix 2.8 1 3 7 pll supply current streaming 1080p30 i dd _pll 2.8 6 7.4 8.5 slvs supply current streaming 1080p30 i dd _slvs 0.4 3 9 14 power (mw) 211.8 323.72 468 7. operating currents are measured in ma at the following conditions: ? v aa = v aa _pix = v dd _pll =2.8 v ? v dd = v dd _io= 1.8 v ? v dd _slvs= 0.4v ? pll enabled and pixclk = 74.25 mhz ? 4?lane hispi mode ? low power mode enabled ? t a = 25 c table 15. 1080p30 hdr (altm) 74 mhz hispi hivcm (low power mode) definition condition symbol voltage min typ max digital operating current streaming 1080p30 i dd 1.8 145 175 235 analog operating current streaming 1080p30 i aa 2.8 25 46 65 pixel supply current streaming 1080p30 i aa _ pix 2.8 1 4 7 pll supply current streaming 1080p30 i dd _pll 2.8 6 7.4 8.5 slvs supply current streaming 1080p30 i dd _slvs 1.8 10 20 30 power (mw) 368.6 511.72 702.4 8. operating currents are measured in ma at the following conditions: ? v aa = v aa _pix = v dd _pll =2.8 v ? v dd = v dd _io = v dd _slvs = 1.8 v ? pll enabled and pixclk = 37.125 mhz ? 4?lane hispi mode ? low power mode enabled ? t a = 25 c table 16. 1080p30 linear 74mhz hispi hivcm definition condition symbol voltage min typ max digital operating current streaming 1080p30 i dd 1.8 75 115 155 analog operating current streaming 1080p30 i aa 2.8 20 30 50 pixel supply current streaming 1080p30 i aa_ pix 2.8 1 3 7 pll supply current streaming 1080p30 i dd _pll 2.8 6 7.4 8.5 slvs supply current streaming 1080p30 i dd _slvs 1.8 10 20 30 power (mw) 228.6 356.12 516.4 9. operating currents are measured in ma at the following conditions: ? v aa = v aa _pix = v dd _pll =2.8 v ? v dd = v dd _io = v dd _slvs= 1.8 v ? pll enabled and pixclk = 74.25 mhz ? 4?lane hispi mode ? low power mode enabled ? t a = 25 c
ar0230cs www. onsemi.com 20 table 17. line interleaved hispi slvs definition condition symbol voltage min typ max digital operating current streaming 1080p30 i dd 1.8 185 230 265 analog operating current streaming 1080p30 i aa 2.8 20 36 55 pixel supply current streaming 1080p30 i aa _pix 2.8 1 3.3 7 pll supply current streaming 1080p30 i dd _pll 2.8 7 8.2 9.5 slvs supply current streaming 1080p30 i dd _slvs 0.4 3 9 14 power (mw) 412.6 550.6 668.8 10. operating currents are measured in ma at the following conditions: ? v aa = v aa _pix = v dd _pll =2.8 v ? v dd = v dd _io= 1.8 v ? v dd _slvs= 0.4 v ? pll enabled and pixclk = 74.25 mhz ? 4?lane hispi mode ? t a = 25 c table 18. line interleaved hispi hivcm definition condition symbol voltage min typ max digital operating current streaming 1080p30 i dd 1.8 185 230 265 analog operating current streaming 1080p30 i aa 2.8 20 36 55 pixel supply current streaming 1080p30 i aa _ pix 2.8 1 3.3 7 pll supply current streaming 1080p30 i dd _pll 2.8 7 8.2 9.5 slvs supply current streaming 1080p30 i dd _slvs 1.8 10 20 30 power (mw) 429.4 583 717.2 11. operating currents are measured in ma at the following conditions: ? v aa = v aa _pix = v dd _pll = 2.8 v ? v dd = v dd _io = 1.8 v ? v dd _slvs = 1.8 v ? pll enabled and pixclk = 74.25 mhz ? 4?lane hispi mode ? t a = 25 c hispi electrical specifications the on semiconductor ar0230cs sensor supports both slvs and hivcm hispi modes. refer to the high?speed serial pixel (hispi) interface physical layer specification v2.00.00 for electrical definitions, specifications, and timing information. the v dd _slvs supply in this datasheet corresponds to v dd _tx in the hispi physical layer specification. similarly, v dd is equivalent to v dd _hispi as referenced in the specification. the dll as implemented on ar0230cs is limited in the number of available delay steps and differs from the hispi specification as described in this section. table 19. channel skew (measurement conditions: _v dd _hispi = 1.8v;v dd _hispi_tx = 0.4v; data rate = 480 mbps; dll set to 0) data lane skew in reference to clock tchskew1phy ?150 ps
ar0230cs www. onsemi.com 21 power?on reset and standby timing power?up sequence the recommended power?up sequence for the ar0230cs is shown in figure 11. the available power supplies (v dd_ io, v dd , v dd_ slvs , v dd _pll, v aa , v aa_ pix) must have the separation specified below. 1. turn on v dd_ pll power supply. 2. after 100 s, turn on v aa and v aa_ pix power supply. 3. after 100 s, turn on v dd _io power supply. 4. after 100 s, turn on vdd power supply. 5. after 100 s, turn on vdd_slvs power supply. 6. after the last power supply is stable, enable extclk. 7. assert reset_bar for at least 1ms. the parallel interface will be tri?stated during this time. 8. wait 150000 extclks (for internal initialization into software standby. 9. configure pll, output, and image settings to desired values. 10. wait 1ms for the pll to lock. 11. set streaming mode (r0x301a[2] = 1). figure 11. power up t hard reset internal initialization software standby pll lock streaming v dd _pll (2.8) v aa _pix v aa _(2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _slvs (0.4) extclk reset_bar tx 0 t 1 t 2 t 3 t 4 t 5 t 6 table 20. power?up sequence definition symbol minimum typical maximum unit v dd_ pll to v aa/ v aa_ pix t0 0 100 ? s v aa/ v aa_ pix to v dd_ io t1 0 100 ? s v dd_ io to v dd t2 0 100 ? s v dd to v dd_ slvs t3 0 100 ? s xtal settle time tx ? 30 ? ms hard reset t4 1 ? ? ms internal initialization t5 150000 ? ? extclks pll lock time t6 1 ? ? ms 12. xtal settling time is component?dependent, usually taking about 10 ? 100 ms. 13. hard reset time is the minimum time required after power rails are settled. in a circuit where hard reset is held down by rc circuit, then the rc time must include the all power rail settle time and xtal settle time. 14. it is critical that v dd _pll is not powered up after the other power supplies. it must be powered before or at least at the same time as the others. if the case happens that v dd _pll is powered after other supplies then sensor may have functionality issues and will experience high current draw on this supply.
ar0230cs www. onsemi.com 22 power?down sequence the recommended power?down sequence for the ar0230cs is shown in figure 12. the available power supplies (v dd_ io, v dd , v dd_ slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. disable streaming if output is active by setting standby r0x301a[2] = 0 2. the soft standby state is reached after the current row or frame, depending on configuration, has ended. 3. turn off v dd _slvs. 4. turn off v dd . 5. turn off v dd _io. 6. turn off v aa /v aa _pix. 7. turn off v dd _pll. figure 12. power down v dd _slvs (0.4) t 4 v dd (1.8) v dd_ io(1.8/2.8) v aa_ pix v aa (2.8) v dd_ pll (2.8) extclk 3 t 2 t 1 t 0 t power down until next power up cycle table 21. power?down sequence definition symbol minimum typical maximum unit v dd_ slvs to v dd t0 0 ? ? s v dd to v dd_ io t1 0 ? ? s v dd_ io to v aa/ v aa_ pix t2 0 ? ? s v aa/ v aa_ pix to v dd_ pll t3 0 ? ? s power down until next power up time t4 100 ? ? ms t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.
ar0230cs www. onsemi.com 23 ibga80 10x10 case 503an issue o
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